* Digitronix Nepal (updated 2024-11-25) ~ youtor.org

Digitronix Nepal (updated 2024-11-25)

ZedBoard FMC HDMI with Real Time Sobel Edge Detection [upl. by Yates507]

ZedBoard FMC HDMI with Real Time Sobel Edge Detection

Duration: 4:39
1.7K views | 19 Apr 2019

Embedded Tutorial Series AVR KEYPAD4x4 LCD Tutorial from Digitronix Nepal [upl. by Acinhoj]

Embedded Tutorial Series AVR KEYPAD4x4 LCD Tutorial from Digitronix Nepal

Duration: 1:06
358 views | 23 Mar 2015

ADC interfacing with 8085 [upl. by Bainter216]

ADC interfacing with 8085

Duration: 1:11
1.1K views | 26 Dec 2016

Anti Collision SystemDEMO [upl. by Darcey]

Anti Collision SystemDEMO

Duration: 0:58
555 views | 17 Sep 2015

Xilinx VIVADO 20154 Creating open example design [upl. by Bettye644]

Xilinx VIVADO 20154 Creating open example design

Duration: 19:14
3.8K views | 24 Feb 2016

Zybo FPGA Video Streaming with VHDL and VIVADO 4K Video [upl. by Eiramasil]

Zybo FPGA Video Streaming with VHDL and VIVADO 4K Video

Duration: 1:16
1.9K views | 10 Jul 2018

DAC interfacing with 8085 [upl. by Akimrehs]

DAC interfacing with 8085

Duration: 0:59
2.1K views | 26 Dec 2016

Real Time Video EncryptionDecryption on Zybo FPGA [upl. by Wester]

Real Time Video EncryptionDecryption on Zybo FPGA

Duration: 1:39
575 views | 21 Feb 2019

Vending Machine Design and Implementation on VHDL amp Xilinx FPGA [upl. by Tecu]

Vending Machine Design and Implementation on VHDL amp Xilinx FPGA

Duration: 1:20
2.1K views | 19 Jul 2018

Binary Clock implemented on Spartan 3E FPGANational FPGA Design Contest 2016 [upl. by Erde]

Binary Clock implemented on Spartan 3E FPGANational FPGA Design Contest 2016

Duration: 3:48
154 views | 8 Jul 2016

YoloV3 Caffe for Object Detection with DPU DNNDK and Ultra96 FPGA [upl. by Donnelly636]

YoloV3 Caffe for Object Detection with DPU DNNDK and Ultra96 FPGA

Duration: 2:03
982 views | 9 Aug 2019

Sobel Edge Detection on Real Time Video with Zyqn FPGA [upl. by Zadack]

Sobel Edge Detection on Real Time Video with Zyqn FPGA

Duration: 2:06
651 views | 25 Aug 2018

Neural Net implementation on Python on Pynq FPGA Digitronix Nepal Tutorial Series on FPGA [upl. by Ylera888]

Neural Net implementation on Python on Pynq FPGA Digitronix Nepal Tutorial Series on FPGA

Duration: 21:14
2.5K views | 19 Jan 2017

Embedded System Design with Xilinx VIVADO amp Zynq FPGA Course at Udemycom [upl. by Smitt]

Embedded System Design with Xilinx VIVADO amp Zynq FPGA Course at Udemycom

Duration: 2:02
460 views | 2 May 2017

Partial Reconfiguration Debugging PR design with ILA and VIO [upl. by Parnell]

Partial Reconfiguration Debugging PR design with ILA and VIO

Duration: 11:01
520 views | 13 Sep 2019

SDSoC Development with Zynq FPGA An Online Course [upl. by Amadeo]

SDSoC Development with Zynq FPGA An Online Course

Duration: 4:46
357 views | 11 Apr 2018

Running Vivado Tcl Scripts of Different Version of VIVADO and Zedboard DMA Audio Demo [upl. by Ponce241]

Running Vivado Tcl Scripts of Different Version of VIVADO and Zedboard DMA Audio Demo

Duration: 14:12
2.5K views | 31 Jan 2017

How to write 12Ghs Keccak algorithm on VHDL targeting VCU1525 [upl. by Nehtanoj]

How to write 12Ghs Keccak algorithm on VHDL targeting VCU1525

Duration: 30:20
1.7K views | 25 Feb 2019

Zynq TRD ported to Zedboard Sobel Filter Implementation with VIVADO HLS by Digitronix Nepal [upl. by Esiuol306]

Zynq TRD ported to Zedboard Sobel Filter Implementation with VIVADO HLS by Digitronix Nepal

Duration: 6:39
599 views | 11 Dec 2017

Webinar Series on FPGA Computer Vision amp Machine Learning with FPGA Feb 17 2019 [upl. by Jereme]

Webinar Series on FPGA Computer Vision amp Machine Learning with FPGA Feb 17 2019

Duration: 50:35
950 views | 18 Feb 2019

Advance Verilog Design Overview Data Types Syntax and Semantics [upl. by Delcine26]

Advance Verilog Design Overview Data Types Syntax and Semantics

Duration: 22:06
410 views | 3 Mar 2019

Interfacing Zedboard FMCHDMI amp Zybo FPGA for Video Processing [upl. by Bernstein]

Interfacing Zedboard FMCHDMI amp Zybo FPGA for Video Processing

Duration: 2:51
1.3K views | 23 Feb 2019

MATLAB based OFDM Receiver Design and Simulation Session [upl. by Edia]

MATLAB based OFDM Receiver Design and Simulation Session

Duration: 14:01
5.8K views | 22 Feb 2019

Vending Machine Design amp Implemented on Spartan 3E Nexys 2FPGA [upl. by Esyli]

Vending Machine Design amp Implemented on Spartan 3E Nexys 2FPGA

Duration: 3:57
767 views | 8 Jul 2016

Conditional Statements in Verilog always block Ifelse amp case statement [upl. by Akir]

Conditional Statements in Verilog always block Ifelse amp case statement

Duration: 25:54
2.3K views | 18 Feb 2019

Groestl Algorithm Explained for CryptoMining Application [upl. by Rhyner]

Groestl Algorithm Explained for CryptoMining Application

Duration: 2:02
218 views | 27 Mar 2019

Partial Reconfiguration with Xilinx VIVADO toolAn Example Design [upl. by Hubie171]

Partial Reconfiguration with Xilinx VIVADO toolAn Example Design

Duration: 9:12
3.5K views | 22 Jul 2019

Numato Mimas V2 Building Github Project of VGA amp Seven Segment [upl. by Aleek118]

Numato Mimas V2 Building Github Project of VGA amp Seven Segment

Duration: 10:41
1.8K views | 20 Apr 2019

Hello World OpenCL acceleration on Xilinx Alveo with Nimbix Cloud [upl. by Eliam]

Hello World OpenCL acceleration on Xilinx Alveo with Nimbix Cloud

Duration: 27:42
2K views | 7 Mar 2019

Custom IP Upload to Zedboard Revision D in QSPI JTAG Mode via Xilinx VIVADO SDK [upl. by Aiciled]

Custom IP Upload to Zedboard Revision D in QSPI JTAG Mode via Xilinx VIVADO SDK

Duration: 3:07
2.3K views | 20 Jan 2017

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